ASIC Design Engineer

Silicon Architect

Designing high-performance, low-power ASICs from RTL to tapeout. Specializing in custom digital logic, timing closure, and physical design.

RTL Design STA / Timing Physical Design DFT Verilog / SystemVerilog

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28nm smallest node

5+ tapeouts

1GHz+ designs closed

// PROJECTS

High-Speed SerDes PHY

28nm CMOS Taped Out

Designed and implemented a 10 Gbps SerDes transceiver for high-bandwidth interconnects. Delivered full RTL, co-designed with analog team for PLL and CDR integration. Achieved timing closure at 1.2 GHz core clock with <5% hold violations on first pass.

ToolsCadence Genus · Innovus · Virtuoso

LangSystemVerilog · UVM

RoleRTL Lead / Physical Design

Low-Power AI Inference Engine

7nm FinFET Taped Out

Architected a systolic array–based neural network accelerator targeting <5mW at peak throughput. Full custom datapath with clock gating, power domains, and UPF low-power flow. Delivered 120 GOPS/W efficiency on ResNet-50 benchmark.

ToolsSynopsys DC · ICC2 · PrimeTime

LangSystemVerilog · UPF · Python

RoleArchitecture · RTL · STA

PCIe Gen5 Controller

12nm IP Block

Developed the transaction and data link layer RTL for a PCIe 5.0 host controller. Implemented TLP reordering logic and flow control with zero-cycle throughput loss. Full DFT insertion including scan chains, MBIST, and LBIST coverage >98%.

ToolsMentor Tessent · Cadence JasperGold

LangVerilog · SystemVerilog Assertions

RoleRTL Design · DFT · Formal Verification

Open-Source RISC-V Core

FPGA / TSMC 65nm Open Source

Personal project — a 5-stage pipelined RV32I core with branch prediction and forwarding paths. Verified with RISC-V compliance test suite. Synthesized to Xilinx Artix-7 at 100 MHz. ASIC implementation targeting TSMC 65nm using OpenLane flow.

ToolsOpenLane · Verilator · GTKWave

LangVerilog · Python (testbench)

Linkgithub.com/yourhandle/riscv-core ↗

Silicon Architect

High-Speed SerDes PHY

Low-Power AI Inference Engine

PCIe Gen5 Controller

Open-Source RISC-V Core

Let's build something at the silicon level.